This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-202552, filed Jul. 3, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a clock synchronous circuit suitable for clock synchronous memories subjected to a synchronous control using a high-speed clock, such as a double data rate (DDR) type DRAM, synchronous DRAM (SDRAM) and double data rate fast cycle RAM (FCRAM).
2. Description of the Related Art
In recent years, in a computer system, clock synchronous memories such as a synchronous DRAM have sometimes been used because of a demand for the raising of a processing speed. For this clock synchronous memory, a clock synchronized with a clock (hereinafter referred to as an xe2x80x9cexternal clockxe2x80x9d) for controlling the memory is also used inside the memory.
However, when a deviation (skew) is generated between the clock (hereinafter referred to as an xe2x80x9cinternal clock) for use in the memory and the external clock because of influences of a receiver (input buffer), an internal circuit of the memory easily causes a malfunction even with a slight deviation particularly in a high-speed operation. Moreover, data outputted from the memory using the internal clock having the deviation from the external clock hinders a high-speed processing even for a controller in which the data is used.
To solve the problem, in recent years, for the memory, a clock synchronous circuit for synchronizing the internal clock with the external clock with a high precision has been disposed in a chip.
For a constitution of the clock synchronous circuit, two types consisting of a periodic type and phase comparison type have heretofore been known. In particular, synchronous traced backward delay (STBD) as a periodic clock synchronous circuit has a high synchronization speed (speed from when power is turned on until synchronization of the external clock with the internal clock is completed) as compared with a phase comparing clock synchronous circuit. Therefore, power-down is frequently performed, and power consumption can be saved.
FIG. 1 shows a block constitution of a conventional periodic clock synchronous circuit.
An external clock EXTCLK is inputted into a receiver (input buffer) 11 having a delay amount Trc. The receiver 11 outputs a clock CLKSTIN which has a skew of Trc with respect to the external clock EXTCLK. The clock CLKSTIN is inputted into a delay monitor 12 having a delay amount Trc+Tdr and a control pulse generating circuit 13.
The delay monitor 12 outputs a forward pulse FCLIN based on the clock CLKSTIN. The control pulse generating circuit 13 outputs control pulses P, bP based on the clock CLKSTIN. The control pulse generating circuit 13 is constituted, for example, of a circuit shown in FIG. 6.
The forward pulse FCLIN is given to a delay line for the forward pulse 14. The delay line for the forward pulse 14 is constituted of N forward delay units 14-1, 14-2, . . . 14-n, . . . 14-N connected in series. Additionally, N and n are both positive numbers, and n less than N.
Operations of the N forward delay units 14-1, 14-2, . . . 14-n, . . . 14-N are controlled in accordance with the control pulses (forward pulse transmission control signals) P, bP. When the N forward delay units 14-1, 14-2, . . . 14-n, . . . 14-N are in an operative state (a state in which the forward pulses can be transmitted), each forward delay unit transmits the forward pulse received from the forward delay unit of a previous stage to the forward delay unit of a subsequent stage.
The forward delay unit 14-n is constituted, for example, of a circuit shown in FIG. 2.
A state-holding section 15 is disposed adjacent to the forward pulse delay line 14. N state-holding units 15-1, 15-2, . . . 15-n, . . . 15-N are associated with the N forward delay units 14-1, 14-2, . . . 14-n, . . . 14-N.
The forward delay unit into which the forward pulse is inputted changes a state (set/reset) of the corresponding state-holding unit. Concretely, all the state-holding units 15-1, 15-2, . . . 15-n, . . . 15-N are in a reset (R) state before the forward pulse FCLIN is inputted into the forward pulse delay line 14. The state-holding unit corresponding to the forward delay unit into which the forward pulse is inputted changes to a set (S) state from the reset (R) state.
The state-holding unit 15-n is constituted, for example, of a circuit shown in FIG. 3.
The N state-holding units 15-1, 15-2, . . . 15-n, . . . 15-N in the state-holding section 15 are returned to the reset state by the control pulse (state-holding section reset signal) bP. Moreover, a state-holding section initializing circuit 17 outputs an initializing signal bRSINI based on the reset signal RESET, and forcibly initializes the states of the N state-holding units 15-1, 15-2, . . . 15-n, . . . 15-N.
The state-holding section initializing circuit 17 is constituted, for example, of a circuit shown in FIG. 4.
Additionally, the delay monitor 12, control pulse generating circuit 13, forward pulse delay line 14, state-holding section 15 and state-holding section initializing circuit 17 have an object of monitoring a delay time xcfx84xe2x88x92(Trc+Tdr) required for synchronizing the external clock EXTCLK with the internal clock INTCLK, and these will be referred to as a monitor circuit.
The monitor circuit monitors the delay time xcfx84xe2x88x92(Trc+Tdr), whereas a delay line for a backward pulse 16 has an object of accurately copying the delay time xcfx84xe2x88x92(Trc+Tdr) monitored by the monitor circuit.
The backward pulse delay line 16 has an object of accurately copying the delay time xcfx84xe2x88x92(Trc+Tdr), and is therefore a complete copy of the forward pulse delay line 14. That is, the forward and backward pulse delay lines 14 and 16 are symmetrically disposed with respect to the state-holding section 15, and completely have the same circuit constitution. Therefore, the STBD of this example is sometimes called a mirror type STBD.
The backward pulse delay line 16 is constituted of N backward delay units 16-1, 16-2, . . . 16-n, . . . 16-N connected in series. The backward pulse delay line 16 accurately copies the delay time xcfx84xe2x88x92(Trc+Tdr) based on the states of the N state-holding units 15-1, 15-2, . . . 15-n, . . . 15-N in the state-holding section 15 and clock CLKSTIN, and subsequently outputs a clock STCLK.
The backward delay unit 16-n is constituted, for example, of the circuit shown in FIG. 5.
The clock STCLK is passed through a driver 18 having a delay amount Tdr, and is then turned into an internal clock INTCLK synchronized with the external clock EXTCLK.
A synchronous operation principle in the STBD will next be described.
Here, similarly as the STBD shown in FIG. 1, the n-th stage forward delay unit 14-n changes the state of the n-th stage state-holding unit 15-n, and the backward delay unit 16-(nxe2x88x921) of an nxe2x88x921st stage operates based on the state of the n-th stage state-holding unit 15-n.
FIG. 7 is a waveform diagram showing the synchronous operation principle of the STBD.
A case in which the external clock EXTCLK shown in FIG. 7 and having a period xcfx84 is inputted into the receiver 11 will be described.
The external clock EXTCLK has a waveform shaped and amplified by the receiver 11, and is outputted as the clock CLKSTIN. Assuming that the delay time of the receiver 11 is Trc, the clock CLKSTIN is delayed from the external clock EXTCLK by Trc (FIG. 7).
The clock CLKSTIN outputted from the receiver 11 is inputted into the delay monitor (mimic delay) 12, control pulse generating circuit 13, and backward pulse delay line 16, respectively.
The control pulse generating circuit 13 forms the clock CLKSTIN into a pulse, and generates a control pulse P which rises in synchronization with the clock CLKSTIN. For example, the period of the control pulse P is set to xcfx84, and the pulse width thereof is set to Wp (FIG. 7). Additionally, the control pulse bP is a reverse signal of the control pulse P.
The delay monitor 12 has a delay time (Trc+Tdr) equal to a total of the delay time Trc of the receiver 11 and delay time Tdr of the driver 18. Therefore, the forward pulse FCLIN outputted from the delay monitor 12 is delayed from the clock CLKSTIN outputted from the receiver 11 by (Trc+Tdr), and inputted into the forward pulse delay line 14 (FIG. 7).
The forward pulse delay line 14 is constituted of the N forward delay units 14-1, 14-2, . . . 14-n, . . . 14-N connected in series. When the control pulse P has an xe2x80x9cL (Low)xe2x80x9d level, each of the N forward delay units 14-1, 14-2, . . . 14-n, . . . 14-N receives the forward pulse outputted from the forward delay unit of the previous stage, and transfers the forward pulse to the forward delay unit of the subsequent stage. Moreover, when the control pulse P has a xe2x80x9cH (High)xe2x80x9d level, each of the N forward delay units 14-1, 14-2, . . . 14-n, . . . 14-N stops the transfer of the forward pulse in the forward pulse delay line 14.
That is, the forward pulse FCLIN is transferred in the forward pulse delay line 14 for a period {xcfx84xe2x88x92(Trc+Tdr)} from when the pulse is inputted into the forward pulse delay line 14 until the control pulse P reaches the xe2x80x9cHxe2x80x9d level (FIG. 7).
The state-holding section 15 stores the transfer state of the forward pulse, and controls the operation of each backward delay unit in the backward pulse delay line 16 based on the information so that a transfer time of the backward pulse in the backward pulse delay line 16 is the same as the transfer time of the forward pulse in the forward pulse delay line 14.
The state-holding section 15 can take two states consisting of the set (S) and reset (R) states, and outputs control signals to the backward delay unit in accordance with the states.
The backward delay unit controlled by the state-holding unit brought into the set state outputs an output signal of the backward delay unit disposed in the subsequent stage as such to the backward delay unit disposed in the previous stage. The backward delay unit controlled by the state-holding unit kept in the reset state outputs the output signal of the receiver 11 to the backward delay unit disposed in the previous stage.
In the state-holding section 15 having an initial state, all the state-holding units 15-1, 15-2, . . . 15-n, . . . 15-N are brought into the reset state by the state-holding section initializing circuit 17. The state-holding unit corresponding to the forward delay unit into which the forward pulse is not inputted keeps the reset state as it is. The state-holding unit corresponding to the forward delay unit into which the forward pulse is inputted has the set state.
When the control pulse P reaches the xe2x80x9cHxe2x80x9d level, the clock CLKSTIN also has the xe2x80x9cHxe2x80x9d level (FIG. 7). Therefore, an input signal (CLKSTIN) having the xe2x80x9cHxe2x80x9d level is inputted into the backward delay unit controlled by the state-holding unit in the reset state (e.g., the backward delay unit in and after the n-th stage of FIG. 26).
Assuming that the number of stages of forward delay units with the forward pulses transferred thereto is n, the state-holding units 15-1, 15-2, . . . 15-n in the first to n-th stages are in the set state. Therefore, the backward pulse is generated in the backward delay unit 16-n of the n-th stage controlled by the state-holding unit of the (n+1)-th stage in the reset state, and transferred to the backward delay unit 16-(nxe2x88x921) of the previous stage from the backward delay unit 16-n.
Therefore, the number of stages of backward delay units with the backward pulses transferred thereto becomes equal to the number of stages of forward delay units with the forward pulses transferred thereto.
Here, the transfer time (delay time) of the forward pulse in the forward pulse delay line 14 and the transfer time (delay time) of the backward pulse in the backward pulse delay line 16 are designed to be equal to each other. Therefore, a time from when the forward pulse FCLIN is inputted into the forward pulse delay line 14 until the backward pulse delay line 16 outputs a backward pulse STCLK is {xcfx84xe2x88x92(Trc+Tdr)}xc3x972 (FIG. 7).
Subsequently, the backward pulse (clock) STCLK outputted from the backward pulse delay line 16 is inputted into the driver 18. Since the driver 18 has a delay time Tdr, the output signal of the driver 18 is the internal clock INTCLK synchronized with the external clock EXTCLK (FIG. 7).
A delay time from when the external clock EXTCLK is inputted into the receiver 11 until the internal clock INTCLK is outputted from the driver 18 is calculated as xcex94total as follows:
xcex94total=xcex94msr+xcex94prpxe2x80x83xe2x80x83(1).
Here, xcex94msr is a time from when the forward pulse is inputted into the delay monitor 12 until the transfer of the forward pulse in the forward pulse delay line 14 is blocked, and xcex94prp is a total time of a time from when the transfer of the forward pulse in the forward pulse delay line 14 is blocked until the backward pulse generated in the backward pulse delay line 16 is outputted from the driver 18 and the delay amount of the receiver 11.
Moreover, assuming that the delay monitor 12 has a delay amount of (Trc+Tdr), and the time of transfer of the forward pulse in the forward pulse delay line 14 is {xcfx84xe2x88x92(Trc+Tdr)}, xcex94msr is represented by the following equation (2).
xcex94msr=(Trc+Tdr)+{xcfx84xe2x88x92(Trc+Tdr)}=xcfx84xe2x80x83xe2x80x83(2)
Furthermore, assuming that the receiver 11 has a delay amount Trc, the driver 18 has a delay amount Tdr, and the time of transfer of the backward pulse in the backward pulse delay line 16 is {xcfx84xe2x88x92(Trc+Tdr)}, xcex94prp is represented by the following equation (3).
xcex94prp=Trc+{xcfx84xe2x88x92(Trc+Tdr)}+Tdr=xcfx84xe2x80x83xe2x80x83(3)
In the equation (3), xcex94prp results in xcfx84 and, as a result, the internal clock INTCLK is synchronized with the external clock EXTCLK.
Additionally, according to the equations (1) to (3) , a time required from when the external clock EXTCLK is inputted into a chip (concretely, the receiver 11) until the internal clock INTCLK synchronized with the external clock EXTCLK is generated is 2xcfx84.
In this manner, in the STBD as the periodic clock synchronous circuit, the time from when the external clock EXTCLK is inputted into the chip until the internal clock INTCLK is generated is as short as 2xcfx84. A synchronous speed (speed from when power is turned on until the synchronization of the external clock with the internal clock is completed) is high, as compared with the phase comparing clock synchronous circuit. Therefore, there are some periods when the memory is unused. Even when the period is very short, the power-down is performed for each period, and power consumption can be reduced.
Additionally, in the conventional periodic clock synchronous circuit, when the memory is continuously used, a monitor operation is performed only once in several cycles of the external clock EXTCLK. The state of the state-holding section 15 obtained in the monitor operation is fixed for several cycles of the external clock EXTCLK. Thereby, the power consumption can further be reduced.
However, there are some problems in this method.
That is, when the memory is operated in actual, a period fluctuation is generated in the external clock EXTCLK, and temperature around the chip changes. In this case, the number of stages of forward delay units through which the forward pulses are transferred is not constant, and changes in accordance with the period fluctuation of the external clock EXTCLK, the temperature around the chip, and the like.
Therefore, when the state of the state-holding section 15 is fixed for several cycles of the external clock EXTCLK, synchronization deviation is generated between the external clock EXTCLK and the internal clock INTCLK for the several cycles, and both the clocks cannot be synchronized with a high precision.
For example, as shown in FIG. 8, the transfer stage number of forward pulses in a k+1 cycle is increased by xcex4 by influences of temperature fluctuation with respect to the transfer stage number of forward pulses in a k cycle. In this case, when the external clock EXTCLK is monitored every cycle, the internal clock INTCLK synchronized with the external clock EXTCLK is constantly obtained, and there is no problem. However, when the external clock EXTCLK is not monitored every cycle, the internal clock INTCLK synchronized with the external clock EXTCLK is not obtained.
Moreover, as shown in FIG. 9, the transfer stage number of forward pulses in the k+1 cycle is decreased by xcex4 by the influences of temperature fluctuation with respect to the transfer stage number of forward pulses in the k cycle. Also in this case, when the external clock EXTCLK is monitored every cycle, the internal clock INTCLK synchronized with the external clock EXTCLK is constantly obtained, and there is no problem. However, when the external clock EXTCLK is not monitored every cycle, the internal clock INTCLK synchronized with the external clock EXTCLK is not obtained.
When the monitor operation is performed every cycle in this manner, the synchronization precision can be enhanced, but the power consumption increases. Conversely, when the monitor operation is performed every several cycles, the power consumption decreases, but the synchronization precision lowers.
In recent years, a change of the transfer stage number of forward pulses by the influences of temperature fluctuation has tended to decrease. In actual, in consideration of the power consumption and synchronization precision, the monitor operation is performed periodically (every cycle or every plurality of cycles).
Moreover, in FIG. 9, when the external clock EXTCLK is monitored periodically, for example, every cycle, at least the n-th and n+1st stage state-holding units have to be in the reset (R) state in the k+1 cycle.
That is, the transfer stage number of the forward pulse in the k+1 cycle decreases by xcex4 with respect to the transfer stage number of the forward pulse in the k cycle. Therefore, the number of state-holding units in the set (S) state has to be decreased in accordance with the decrease of the transfer stage number. Therefore, before the k+1 cycle starts, the state-holding units corresponding to xcex4 (surrounded by a broken line in FIG. 9) or the state-holding units including xcex4 (units before the nxe2x88x921st stage) need to be returned to the reset state from the set state (this operation will be described hereinafter as a xe2x80x9creset operationxe2x80x9d).
In the STBD among the periodic clock synchronous circuits (STBD, SMD, and the like), the state-holding units 15-1, 15-2, . . . 15-n, . . . 15-N in the state-holding section 15 have latch circuits.
As the latch circuits, a dynamic latch circuit whose state can be held only for a constant time, and a static latch circuit whose state is always held as long as the circuit is not reset can be used. In either one of the latch circuits, particularly the case of FIG. 9 is considered. After the monitor operation is performed, the reset operation is performed, preparing for the next monitor operation. It is necessary to reset the states of the state-holding units 15-1, 15-2, . . . 15-n, . . . 15-N in the state-holding section 15.
Additionally, various methods have heretofore been considered with respect to the reset operation which is performed periodically (every cycle or every plurality of cycles). However, a method of realizing low power consumption, high synchronization precision, simple layout, small circuit size, and the like at the same time has not been proposed yet.
In the clock synchronous circuit in which the latch circuit is used to hold a monitor result for a constant period in this manner, the reset operation of the state-holding unit in the state-holding section and the monitor operation of the clock have to be performed periodically, that is, every cycle or every plurality of cycles of the external clock EXTCLK. However, a clock synchronous circuit for realizing low power consumption, high synchronization precision, simple layout, small circuit size, and the like at the same time has not been proposed yet.
According to one aspect of the present invention, there is provided a clock synchronous circuit which performs a synchronous operation of synchronizing a first clock with a second clock, comprising: a delay line for a forward pulse, which includes a plurality of stages of forward delay units, and uses the forward pulse to monitor a delay time necessary for the synchronous operation; a state-holding section which includes a plurality of stages of state-holding units, holds the delay time by the set/reset state of the plurality of stages of state-holding units; and a delay line for a backward pulse, which includes a plurality of stages of backward delay units, and uses the backward pulse to copy the delay time, wherein each of the plurality of stages of state-holding units is reset on a condition that the state-holding unit of the subsequent stage is in the reset state in a reset period.
According to another aspect of the present invention, there is provided a clock synchronous memory on which the above-described clock synchronous circuit is mounted.
According to another aspect of the present invention, there is provided a memory system comprising: a memory on which the above-described clock synchronous circuit is mounted; a CPU which supplies the second clock to the memory; and a bus which connects the memory to the CPU.